Renesas Electronics /R7FA6M1AD /GPT_ODC /GTDLYR1B

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as GTDLYR1B

15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (others)DLY

DLY=others

Description

GTIOC1B Rising Output Delay Register

Fields

DLY

GTIOCnB Output Rising Edge Delay Setting

0 (00000): No delay on rising edges

0 (others): Delay of DLY/32 times the PCLKD period is applied.

Links

()